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cy7c68053 mobl-usb? fx2lp18 usb microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document # 001-06120 rev *j revised october 28, 2010 1. features usb 2.0 9 v usb-if high speed and full speed compliant (tid# 40000188) single-chip integrated usb 2.0 transceiver, smart sie, and enhanced 8051 microprocessor ideal for mobile applications (cell phone, smart phones, pdas, mp3 players) ? ultra low power ? suspend current: 20 a (typical) software: 8051 code runs from: ? internal ram, which is loaded from eeprom 16 kbytes of on-chip code/data ram four programmable bulk/interrupt/isochronous endpoints ? buffering options: double, triple, and quad additional programmable (bulk/interrupt) 64-byte endpoint 8 or 16-bit external data interface smart media standard ecc generation gpif (general programmable interface) ? allows direct connection to most parallel interface ? programmable waveform descriptors and configuration registers to define waveforms ? supports multiple ready and control outputs integrated, industry standard enhanced 8051 ? 48 mhz, 24 mhz, or 12 mhz cpu operation ? four clocks per instruction cycle ? three counter/timers ? expanded interrupt system ? two data pointers 1.8 v core operation 1.8 v to 3.3 v i/o operation vectored usb interrupts and gpif/fifo interrupts separate data buffers for setup and data portions of a control transfer integrated i 2 c controller, runs at 100 or 400 khz four integrated fifos ? integrated glue logic and fifos lower system cost ? automatic conversion to and from 16-bit buses ? master or slave operation ? uses external clock or asynchronous strobes ? easy interface to asic and dsp ics available in industrial temperature grade available in one pb-free package with up to 24 gpios ? 56-pin vfbga (24 gpios) x20 pll /0.5 /1.0 /2.0 8051 core 12/24/48 mhz, four clocks/cycle i 2 c vcc 1.5k d+ d? address (16) / data bus (8) gpif cy smart usb 1.1/2.0 engine usb 2.0 xcvr 16 kb ram 4 kb fifo integrated full- and high-speed xcvr additional ios (24) ctl (3) rdy (2) 24 mhz ext. xtal enhanced usb core simplifies 8051 code ?soft configuration? easy firmware changes fifo and endpoint memory (master or slave operation) general programmable i/f abundant io high-performance microprocessor using standard tools with lower-power options master connected for full-speed ecc mobl-usb fx2lp18 to baseband processors/ application processors/ asics/dsps 8/16 up to 96 mbytes/sec burst rate logic block diagram [+] feedback
cy7c68053 document # 001-06120 rev *j page 2 of 42 contents applications ...................................................................... 3 functional overview ........................................................ 3 usb signaling speed ............. .............. .............. ......... 3 8051 microprocessor ... .............. .............. ........... ......... 3 i 2 c? bus .................................................................... 4 buses .......................................................................... 4 usb boot methods ...................................................... 4 renumeration? ..................... ..................................... 4 bus-powered applications ..... ..................................... 4 interrupt system .......................................................... 4 reset and wakeup ...................................................... 6 program/data ram ..................................................... 7 register addresses ..................................................... 7 endpoint ram ............................................................. 7 external fifo interface ............................................... 9 gpif ............................................................................ 9 ecc generation [6] ................................................................... 10 usb uploads and downloads ... .............. ........... ....... 10 autopointer access ................................................... 10 i 2 c controller ............................................................. 10 pin assignments ............................................................ 11 cy7c68053 pin descriptions ................................... 13 register summary .......................................................... 17 absolute maximum ratings .......................................... 24 operating conditions ..................................................... 24 dc characteristics ........................................................ 24 ac electrical characteristics ........................................ 25 usb transceiver ....................................................... 25 gpif synchronous signals ....................................... 25 slave fifo synchronous read ................................. 26 slave fifo asynchronous r ead ............ ........... ........ 27 slave fifo synchronous write ................................. 28 slave fifo asynchronous write ............................... 29 slave fifo synchronous pack et end strobe ........... 29 slave fifo asynchronous packet end strobe ........ 30 slave fifo output enable ....................................... 31 slave fifo address to flags/data ........................... 31 slave fifo synchronous address ........................... 32 slave fifo asynchronous address ......................... 32 sequence diagram .................................................... 33 ordering information ...................................................... 37 ordering code definitions ..... .................................... 37 package diagram ............................................................ 38 pcb layout recommendations .................................... 39 acronyms ........................................................................ 40 document conventions ................................................. 40 units of measure ....................................................... 40 document history page ................................................. 41 sales, solutions, and legal information ...................... 42 worldwide sales and design s upport ......... .............. 42 products .................................................................... 42 psoc solutions ......................................................... 42 [+] feedback
cy7c68053 document # 001-06120 rev *j page 3 of 42 cypress semiconductor corporation?s mobl-usb ? fx2lp18 (cy7c68053) is a low voltage (1.8 v) version of the ez-usb ? fx2lp (cy7c68013a), which is a highly integrated, low power usb 2.0 microcontroller. by inte grating the usb 2.0 transceiver, serial interface engine (sie), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, cypress has created a very cost ef fective solution that provides superior time-to-market advantages with low power to enable bus powered applications. the ingenious architecture of mobl-usb fx2lp18 results in data transfer rates of over 53 mbytes per second, the maximum allowable usb 2.0 bandwidth, while still using a low cost 8051 microcontroller in a package as small as a 56vfbga (5 mm x 5 mm). because it incorporates the usb 2.0 transceiver, the mobl-usb fx2lp18 is more economical, providing a smaller footprint solution than usb 2.0 sie or external transceiver implementations. with mobl-usb fx2lp18, the cypress smart sie handles most of the usb 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure usb compatibility. the general programmable interf ace (gpif) and master/slave endpoint fifo (8 or 16-bit data bus) provide an easy and glueless interface to popular interfaces such as ata, utopia, epp, pcmcia, and most dsp/processors. the mobl-usb fx2lp18 is also referred to as fx2lp18 in this document. 2. applications there are a wide variety of applications for the mobl-usb fx2lp18. it is used in cell phones, smart phones, pdas, and mp3 players, to name a few. the ?reference designs? section of the cypress web site provides additional tools for typical usb 2.0 applications. each reference design comes complete with firmware source and object code, schematics, and documentation. for more information, visit http://www.cypress.com . 3. functional overview the functionality of this chip is described in the sections below. 3.1 usb signaling speed fx2lp18 operates at two of the three rates defined in the usb specification revision 2.0, dated april 27, 2000. full speed, with a signaling bit rate of 12 mbps high speed, with a signaling bit rate of 480 mbps fx2lp18 does not support the low speed signaling mode of 1.5 mbps. 3.2 8051 microprocessor the 8051 microprocessor embedded in the fx2lp18 family has 256 bytes of register ram, an expanded interrupt system, and three timer/counters. 3.2.1 8051 clock frequency fx2lp18 has an on-chip oscillator circuit that uses an external 24 mhz (100-ppm) crystal with the following characteristics: parallel resonant fundamental mode 500 w drive level 12 pf (5% tolerance) load capacitors an on-chip pll multiplies the 24 mhz oscillator up to 480 mhz, as required by the transceiver/phy; internal counters divide it down for use as the 8051 clock. the default 8051 clock frequency is 12 mhz. the clock frequency of the 8051 can be changed by the 8051 through the cpucs register, dynamically. the clkout pin, which can be tristated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency ? 48, 24, or 12 mhz. 3.2.2 special function registers certain 8051 special function register (sfr) addresses are populated to provide fast access to critical fx2lp18 functions. these sfr additions are shown in table 1 on page 4 . bold type indicates non standard, enhanced 8051 registers. the two sfr rows that end with ?0? and ?8? c ontain bit-addressable registers. the four i/o ports a?d use the sfr addresses used in the standard 8051 for ports 0?3, which are not implemented in fx2lp18. because of the faster and more efficient sfr addressing, the fx2lp18 i/o ports are not addressable in external ram space (using the movx instruction). figure 1. crystal configuration 12 pf 12 pf 24 mhz 20 pll c1 c2 12 pf capacitor values assumes a trace capacitance of 3 pf per side on a four-layer fr4 pca [+] feedback
cy7c68053 document # 001-06120 rev *j page 4 of 42 3.3 i 2 c? bus fx2lp18 supports the i 2 c bus as a master only at 100 or 400 khz. scl and sda pins have open-drain outputs and hysteresis inputs. these signals must be pulled up to either v cc or v cc_io , even if no i 2 c device is connected. (connecting to v cc_io may be more convenient.) 3.4 buses this 56-pin package has an 8- or 16-bit ?fifo? bidirectional data bus, multiplexed on i/o ports b and d. 3.5 usb boot methods during the power up sequence, internal logic checks the i 2 c port for the connection of an eeprom whose first byte is 0xc2. if found, it boot-loads the eeprom contents into internal ram (0xc2 load). if no eeprom is pr esent, an external processor must emulate an i 2 c slave. the fx2lp18 does not enumerate using internally stored descriptors (for example, cypress?s vid/pid/did is not us ed for enumeration). [1] 3.6 renumeration? because the fx2lp18?s configuration is soft, one chip can take on the identities of multip le distinct usb devices. when first plugged into usb, the fx2lp18 enumerates automatically and downloads firmware and usb descriptor tables over the usb cable. next, the fx2lp18 enumerates again, this time as a device defined by the downloaded information. this patented two-step process, called renumeration ? , happens instantly when the device is plugged in, with no hint that the initial download step has occurred. two control bits in the usbcs (u sb control and status) register control the renumeration process: discon and renum. to simulate a usb disconnect, the firmware sets discon to 1. to reconnect, the firmware clears discon to 0. before reconnecting, the firmware sets or clears the renum bit to indicate whether the firmware or the default usb device handles device requests over endpoint zero: if renum = 0, the default usb device handles device requests; if renum = 1, the firmware does. 3.7 bus-powered applications the fx2lp18 fully supports bus-powered designs by enumerating with less than 100 ma as required by the usb 2.0 specification. 3.8 interrupt system the fx2lp18 interrupts are described in this section. 3.8.1 int2 interrupt request and enable registers fx2lp18 implements an autovector feature for int2. there are 27 int2 (usb) vectors. see the mobl-usb? technical reference manual (trm) for more details. 3.8.2 usb interrupt autovectors the main usb interrupt is shared by 27 interrupt sources. to save the code and processing time that is normally required to identify the individual usb interrupt source, the fx2lp18 provides a second level of interrupt vectoring, called ?autovectoring.? when a usb inte rrupt is asserted, the fx2lp18 pushes the program counter onto its stack then jumps to address 0x0043, where it expects to find a ?jump? instruction to the usb interrupt service routine. the fx2lp18 jump instruction is encoded as shown in table 2 on page 5 . table 1. special function registers x 8x 9x ax bx cx dx ex fx 0 ioa iob ioc iod scon1 psw acc b 1sp exif int2clr ioe sbuf1 2dpl0 mpage oea 3dph0 oeb 4 dpl1 oec 5 dph1 oed 6 dps oee 7pcon 8 tcon scon0 ie ip t2con eicon eie eip 9 tmod sbuf0 atl0 autoptrh1 ep2468stat ep01stat rcap2l btl1 autoptrl1 ep24fifoflgs gpiftrig rcap2h cth0 reserved ep68fifoflgs tl2 dth1 autoptrh2 gpifsgldath th2 e ckcon autoptrl2 gpifsgldatlx f reserved autoptrset-up gpifsgldatlnox note 1. the i 2 c bus scl and sda pins must be pulled up, even if an eeprom is not connected. otherwise this detect ion method does not work pro perly. [+] feedback
cy7c68053 document # 001-06120 rev *j page 5 of 42 if autovectoring is enabled (av2en = 1 in the intset-up register), the fx2lp18 substitutes its int2vec byte. therefore, if the high byte (?page?) of a jump-table address is preloaded at location 0x0044, the automatical ly inserted int2vec byte at 0x0045 directs the jump to the correct address out of the 27 addresses within the page. table 2. int2 usb interrupts priority int2vec value source notes 1 00 sudav setup data available 2 04 sof start of frame (or microframe) 3 08 sutok setup token received 4 0c suspend usb suspend request 5 10 usb reset bus reset 6 14 hispeed entered high speed operation 7 18 ep0ack fx2lp18 ack?d the control handshake 8 1c reserved 9 20 ep0-in ep0-in ready to be loaded with data 10 24 ep0-out ep0-out has usb data 11 28 ep1-in ep1-in ready to be loaded with data 12 2c ep1-out ep1-out has usb data 13 30 ep2 in: buffer available. out: buffer has data 14 34 ep4 in: buffer available. out: buffer has data 15 38 ep6 in: buffer available. out: buffer has data 16 3c ep8 in: buffer available. out: buffer has data 17 40 ibn in-bulk-nak (any in endpoint) 18 44 reserved 19 48 ep0ping ep0 out was pinged and it nak?d 20 4c ep1ping ep1 out was pinged and it nak?d 21 50 ep2ping ep2 out was pinged and it nak?d 22 54 ep4ping ep4 out was pinged and it nak?d 23 58 ep6ping ep6 out was pinged and it nak?d 24 5c ep8ping ep8 out was pinged and it nak?d 25 60 errlimit bus errors exceeded the programmed limit 26 64 27 68 reserved 28 6c reserved 29 70 ep2isoerr iso ep2 out pid sequence error 30 74 ep4isoerr iso ep4 out pid sequence error 31 78 ep6isoerr iso ep6 out pid sequence error 32 7c ep8isoerr iso ep8 out pid sequence error [+] feedback
cy7c68053 document # 001-06120 rev *j page 6 of 42 3.9 reset and wakeup the reset and wakeup pins are described in detail in this section. 3.9.1 reset pin the input pin, reset#, resets the fx2lp18 when asserted. this pin has hysteresis and is active low. when a crystal is used with the cy7c68053, the reset period must allow for the stabilization of the crystal and the pll. this reset period must be approximately 5 ms after vcc has reached 3.0 v. if the crystal input pin is driven by a clock signal the internal pll stabilizes in 200 s after v cc has reached 3.0 v [2] . figure 2 shows a power on reset condition and a reset applied during operation. a power on reset is defined as the time reset is asserted while power is being applied to the circuit. a powered reset is defined as a reset in which the fx2lp18 has pr eviously been powered on and operating and the reset # pin is asserted. cypress provides an application note which describes and recommends power on reset implementation, which can be found on the cypress web site. for more information on reset implementation for the mobl-usb family of products, visit the cypress web site at http://www.cypress.com . 3.9.2 wakeup pins the 8051 puts itself and the rest of the chip into a power-down mode by setting pcon.0 = 1. this stops the oscillator and pll. when wakeup is asserted by ex ternal logic, the oscillator restarts, after the pll stabilize s, and then the 8051 receives a wakeup interrupt. this applie s whether or not fx2lp18 is connected to the usb. the fx2lp18 exits the power down (usb suspend) state using one of the following methods: usb bus activity (if d+/d? lines are left floating, noise on these lines may indicate activity to the fx2lp18 and initiate a wakeup) external logic asserts the wakeup pin external logic asserts the pa3/wu2 pin the second wakeup pin, wu2, can also be configured as a general purpose i/o pin. this allows a simple external r-c network to be used as a periodic wakeup source. note that wakeup is active low by default. 3.9.3 lowering suspend current good design practices for cmos circuits dictate that any unused input pins must not be floating between v il and v ih . floating input pins will not damage the chip, but can substantially increase suspend current. to achieve the lowest suspend current, confiigure unused port pins as outputs. connect unused input pins to ground. some exampl es of pins that need attention during suspend are: port pins. for port a, b, d pins, take extra care in shared bus situations. ? connect completely unused pins to v cc_io or gnd. ? in a single-master system, the firmware must output enable all the port pins and drive them high or low, before fx2lp18 enters the suspend state. ? in a multi-master system (fx 2lp18 and anoth er processor sharing a common data bus), when fx2lp18 is suspended, the external master must drive the pins high or low. the external master must not let the pins float. clkout. if clkout is not used , it must be tri-stated during normal operation, but driven during suspend. ifclk, rdy0, rdy1. these pins must be pulled to v cc_io or gnd or driven by another chip. figure 2. reset timing plots v il 0 v 1.8 v 1.62 v t reset v cc reset# power on reset t reset v cc reset# v il powered reset 1.8 v 0 v table 3. reset timing values condition t reset power on reset with crystal 5 ms power on reset with external clock 200 s + clock stability time powered reset 200 s note 2. if the external clock is powered at the same time as the cy7c 680xx and has a stabilization wait period, it must be added to t he 200 s. [+] feedback
cy7c68053 document # 001-06120 rev *j page 7 of 42 ctl0-2. if tri-stated via gpifidlectl, these pins must be pulled to v cc_io or gnd or driven by another chip. reset#, wakeup#. these pins must be pulled to v cc_io or gnd or driven by another chip during suspend. 3.10 program/data ram this section describes the fx2lp18 ram. 3.10.1 size the fx2lp18 has 16 kbytes of internal program/data ram. no usb control registers appear in this space. memory maps are shown in figure 3 and figure 4 . 3.10.2 internal code memory this mode implements the internal 16-kbyte block of ram (starting at 0) as combined code and data memory. only the internal 16 kbytes and scratch pad 0.5 kbytes ram spaces have the following access: usb download usb upload setup data pointer i 2 c interface boot load 3.11 register addresses 3.12 endpoint ram this section describes the fx2lp18 endpoint ram. 3.12.1 size 3 64 bytes (endpoints 0, 1) 8 512 bytes (endpoints 2, 4, 6, 8) 3.12.2 organization ep0 bidirectional endpoint zero, 64-byte buffer ep1in, ep1out 64-byte buffers: bulk or interrupt ep2, 4, 6, 8 eight 512-byte buffers: bulk, interrupt, or isochronous. ep4 and ep8 can be double buffered, while ep2 and 6 can be double, triple, or quad buffered. for high speed endpoint configuration options, see figure 5 on page 8 . 3.12.3 setu p data buffer a separate 8-byte buffer at 0xe6b8-0xe6bf holds the setup data from a control transfer. figure 3. fx2lp18 internal code memory 7.5 kbytes usb regs and 4k fifo buffers 0.5 kbytes ram data 16 kbytes ram code and data ffff e200 e1ff e000 3fff 0000 . . . ffff e800 e7bf e740 e73f e700 e6ff e500 e4ff e480 e47f e400 e200 e1ff e000 e3ff efff 2 kbytes reserved 64 bytes ep0 in/out 64 bytes reserved 8051 addressable registers reserved (128) 128 bytes gpif waveforms 512 bytes 8051 xdata ram f000 (512) reserved (512) e780 64 bytes ep1out e77f 64 bytes ep1in e7ff e7c0 4 kbytes ep2-ep8 buffers (8 x 512) figure 4. register address memory [+] feedback
cy7c68053 document # 001-06120 rev *j page 8 of 42 3.12.4 endpoint configurations (high speed mode) endpoints 0 and 1 are the same for every configuration. endpoint 0 is the only control endpoint, and endpoint 1 can be either bulk or interrupt. the endpoint buffers can be configured in any one of the 12 configurations shown in the vertical columns of figure 5 . when operating in full speed bulk mode only the first 64 bytes of each buffer are used. for example, in high speed the maximum packet size is 512 by tes, but in full speed it is 64 bytes. even though a buffer is configured to be a 512 byte buffer, in full speed only the first 64 bytes are used. the unused endpoint buffer space is not available for other operations. an example endpoint configuration is: ep2?1024 double buffered; ep6?512 quad buffered (column 8). 3.12.5 default full speed alternate settings 64 64 64 512 512 1024 1024 1024 1024 1024 1024 1024 512 512 512 512 512 512 512 512 512 512 ep2 ep2 ep2 ep6 ep6 ep8 ep8 ep0 in&out ep1 in ep1 out figure 5. endpoint configuration 1024 1024 ep6 1024 512 512 ep8 512 512 ep6 512 512 512 512 ep2 512 512 ep4 512 512 ep2 512 512 ep4 512 512 ep2 512 512 ep4 512 512 ep2 512 512 512 512 ep2 512 512 512 512 ep2 512 512 1024 ep2 1024 1024 ep2 1024 1024 ep2 1024 512 512 ep6 1024 1024 ep6 512 512 ep8 512 512 ep6 512 512 512 512 ep6 1024 1024 ep6 512 512 ep8 512 512 ep6 512 512 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 1 2 3 4 5 6 7 8 9 10 11 12 table 4. default full speed alternate settings [3, 4] alternate setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 64 bulk 64 int 64 int ep1in 0 64 bulk 64 int 64 int ep2 0 64 bulk out (2) 64 int out (2) 64 iso out (2) ep4 0 64 bulk out (2) 64 bulk out (2) 64 bulk out (2) ep6 0 64 bulk in (2) 64 int in (2) 64 iso in (2) ep8 0 64 bulk in (2) 64 bulk in (2) 64 bulk in (2) notes 3. ?0? means ?not implemented.? 4. ?2? means ?double buffered.? [+] feedback
cy7c68053 document # 001-06120 rev *j page 9 of 42 3.12.6 default high speed alternate settings 3.13 external fifo interface the architecture, control signals, and clock rates are presented in this section. 3.13.1 architecture the fx2lp18 slave fifo architectu re has eight 512-byte blocks in the endpoint ram that directly serve as fifo memories and are controlled by fifo control si gnals (such as ifclk, slcs#, slrd, slwr, sloe, pktend, and flags). in operation, some of the eight ra m blocks fill or empty from the sie while the others are connected to the i/o transfer logic. the transfer logic takes two forms: the gpif for internally generated control signals or the slave fifo interface for externally controlled transfers. 3.13.2 master/slave control signals the fx2lp18 endpoint fifos are implemented as eight physically distinct 256x16 ram bl ocks. the 8051/si e can switch any of the ram blocks between two domains, the usb (sie) domain and the 8051-i/o unit domain. this switching is instantaneous, giving zero transfer time between ?usb fifos? and ?slave fifos?. because th ey are physically the same memory, no bytes are actually transferred between buffers. at any given time, some ram bl ocks are filling and emptying with usb data under sie control, while other ram blocks are available to the 8051, the i/o control unit, or both. the ram blocks operate as single port in the usb domain, and dual port in the 8051-i/o domain. the blocks can be configured as single, double, triple, or quad buffered as previously shown. the i/o control unit implements eit her an internal master (m for master) or external master (s for slave) interface. in master (m) mode, the gpif in ternally controls fifoadr[1:0] to select a fifo. the two ready (rdy) pins can be used as flag inputs from an external fifo or ot her logic. the gpif can be run from either an internally derived clock or externally supplied clock (ifclk), at a rate that transfers data up to 96 megabytes/s (48 mhz ifclk with 16-bit interface). in slave (s) mode, the fx2lp18 accepts either an internally derived clock or externally supplied clock (ifclk, maximum frequency 48 mhz) and slcs#, slrd, slwr, sloe, pktend signals from external logic. when using an external ifclk, the external clock must be present before switching to the external clock with the ifclksrc bit. each endpoint can individually be selected for byte or word operation by an internal configuration bit, and a slave fifo output enable signal (sloe) enables data of the selected width. external lo gic must insure that the output enable signal is inactive when writing data to a slave fifo. the slave interface can also operate asynchronously, where the slrd and slwr signals act directly as strobes, rather than a clock qualifier as in synchronous mode. the signals slrd, slwr, sloe, and pktend are gated by the signal slcs#. 3.13.3 gpif and fifo clock rates an 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 mhz and 48 mhz. alternatively, an externally supplied clock of 5 mhz?48 mhz feeding the ifclk pin can be used as the interface clock. ifclk can be configured to function as an output clock when the gpif and fifos are internally clocked. an output enable bit in the ifconfig register turns this clock output off. another bit within the ifconfig register inverts the ifclk signal whether internally or externally sourced. 3.14 gpif the gpif is a flexible 8- or 16-bit parallel interface driven by a user programmable finite state machine. it allows the cy7c68053 to perform local bus mastering, and can implement a wide variety of protocols such as ata interface, parallel printer port, and utopia. the gpif has three programmable control outputs (ctl), and two general purpose ready inputs.the data bus width can be 8 or 16 bits. each gpif vector defines the state of the control outputs, and determines what state a ready input (or multiple inputs) must be before proceeding. the gpif vector can be programmed to advance a fifo to the next data value, advance an address, and so on. a sequenc e of the gpif vectors makes up a single waveform that is executed to perform the desired data move between the fx2lp18 and the external device. note 5. even though these buffers are 64 bytes, they are reported as 512 for usb 2.0 compliance. nnever transfer packets larger than 64 bytes to ep1. table 5. default high speed alternate settings [3, 4] alternate setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 512 bulk [5] 64 int 64 int ep1in 0 512 bulk [5] 64 int 64 int ep2 0 512 bulk out (2) 512 int out (2) 512 iso out (2) ep4 0 512 bulk out (2) 512 bulk out (2) 512 bulk out (2) ep6 0 512 bulk in (2) 512 int in (2) 512 iso in (2) ep8 0 512 bulk in (2) 512 bulk in (2) 512 bulk in (2) [+] feedback
cy7c68053 document # 001-06120 rev *j page 10 of 42 3.14.1 three control out signals the 56-pin package brings out three of these signals, ctl0?ctl2. the 8051 programs t he gpif unit to define the ctl waveforms. ctlx waveform edges can be programmed to make transitions as fast as once per clock cycle (20.8 ns using a 48 mhz clock). 3.14.2 two ready in signals the fx2lp18 package brings out all two ready inputs (rdy0?rdy1). the 8051 programs the gpif unit to test the rdy pins for gpif branching. 3.14.3 long transfer mode in master mode, the 8051 appropriately sets gpif transaction count registers (g piftcb3, gpiftcb2, gpiftcb1, or gpiftcb0) for unattended transfers of up to 2 32 transactions. the gpif automatically throttles data flow to prevent under or overflow until the full number of requested transactions complete. the gpif decrements th e value in these registers to represent the current status of the transaction. 3.15 ecc generation [6] the mobl-usb can calculate e rror correcting codes (eccs) on data that passes across its gpif or slave fifo interfaces. there are two ecc configurations: tw o eccs, each calculated over 256 bytes (smartmedia standard) and one ecc calculated over 512 bytes. the ecc can correct any 1-bit error or detect any 2-bit error. 3.15.1 ecc implementation the two ecc configurations ar e selected by the eccm bit. 3.15.1.1 eccm = 0 two 3-byte eccs are each calculated over a 256-byte block of data. this configuration confo rms to the smartmedia standard. this configuration writes any value to eccreset, then passes data across the gpif or slave fifo interface. the ecc for the first 256 bytes of data is calculated and stored in ecc1. the ecc for the next 256 bytes is stored in ecc2. after the second ecc is calculated, the values in the eccx registers do not change until eccreset is written again, even if more data is subsequently passed across the interface. 3.15.1.2 eccm = 1 one 3-byte ecc is calculated over a 512-byte block of data. this configuration writes any value to eccreset then passes data across the gpif or slave fifo interface. the ecc for the first 512 bytes of data is calculated and stored in ecc1; ecc2 is unused. after the ecc is calc ulated, the value in ecc1 does not change until eccreset is writ ten again, even if more data is subsequently passed across the interface. 3.16 usb uploads and downloads the core has the ability to directly edit the data contents of the internal 16-kbyte ram and of t he internal 512-byte scratch pad ram using a vendor-specific co mmand. this capability is normally used when ?soft? downloading user code and is available only to and from internal ram, only when the 8051 is held in reset. the available ram spaces are 16 kbytes from 0x0000?0x3fff (code/data) and 512 bytes from 0xe000?0xe1ff (scratch pad data ram). [7] 3.17 autopointer access fx2lp18 provides two identical autopointers. they are similar to the internal 8051 data pointers, but with an additional feature: they can optionally increment after every memory access. the autopointers are available in ex ternal fx2lp18 registers, under control of a mode bit (autoptrset-up.0). using the external fx2lp18 autopointer access (at 0xe67b ? 0xe67c) allows the autopointer to access all ram. also, the autopointers can point to any fx2lp18 register or endpoint buffer space. 3.18 i 2 c controller fx2lp18 has one i 2 c port that is driven by two internal controllers. one controll er automatically operate s at boot time to load the vid/pid/did, configur ation byte, and firmware. the second controller is used by the 8051, once running, to control external i 2 c devices. the i 2 c port operates in master mode only. 3.18.1 i 2 c port pins the i 2 c pins scl and sda must have external 2.2k ohm pull up resistors even if no eeprom is connected to the fx2lp18. the value of the pull up resistors required may vary, depending on the combination of v cc_io and the supply used for the eeprom. the pull up resistors used must be such that when the eeprom pulls sda low, the voltage level meets the v il specification of the fx2lp18. for example, if the eepr om runs off a 3.3 v supply and v cc_io is 1.8 v, the pull up resistors recommended are 10k ohm . this requirement may also vary depending on the devices being run on the i 2 c pins. refer to the i 2 c specifications for details. external eeprom device addre ss pins must be configured properly. see table 6 on page 11 for configuring the device address pins. if no eeprom is connected to the i 2 c port, eeprom emulation is required by an external processor. this is because the fx2lp18 comes out of reset with the discon bit set, so the device will not enumerate without an eeprom (c2 load) or eeprom emulation. notes 6. to use the ecc logic, the gpif or slave fifo interface must be configured for byte-wide operation. 7. after the data is downloaded from the host, a ?loader? can execut e from internal ram in order to transfer downloaded data to external memory. [+] feedback
cy7c68053 document # 001-06120 rev *j page 11 of 42 3.18.2 i 2 c interface boot load access at power on reset the i 2 c interface boot loader loads the vid/pid/did and configuration byte s and up to 16 kbytes of program/data. the available ram spaces are 16 kbytes from 0x0000?0x3fff and 512 bytes from 0xe000?0xe1ff. the 8051 is reset. i 2 c interface boot loads only occur after power on reset. 3.18.3 i 2 c interface general purpose access the 8051 can control peripherals connected to the i 2 c bus using the i2ctl and i2dat registers. fx2lp18 provides i 2 c master control only, it is never an i 2 c slave. 4. pin assignments figure 6 identifies all signals for the package. it is followed by the pin diagram.three modes are available: port, gpif master, and slave fifo. these modes define the signals on the right edge of the diagram. the 8051 selects the interface mode using the ifconfig[1:0] register bits. port mode is the power on default configuration. table 6. strap boot eeprom address lin es to these values bytes example eeprom a2 a1 a0 16 24aa00 [8] n/a n/a n/a 128 24aa01 0 0 0 256 24aa02 0 0 0 4k 24aa32 0 0 1 8k 24aa64 0 0 1 16k 24aa128 0 0 1 note 8. this eeprom does not have address pins. xtalin xtalout reset# wakeup# scl sda ifclk clkout dplus dminus rdy0 rdy1 ctl0 ctl1 ctl2 int0#/pa0 int1#/pa1 pa2 wu2/pa3 pa4 pa5 pa6 pa7 fd[15] fd[14] fd[13] fd[12] fd[11] fd[10] fd[9] fd[8] fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0] slrd slwr flaga flagb flagc int0#/pa0 int1#/pa1 sloe wu2/pa3 fifoadr0 fifoadr1 pktend pa7/flagd/slcs# fd[15] fd[14] fd[13] fd[12] fd[11] fd[10] fd[9] fd[8] fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0] pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 int0#/pa0 int1#/pa1 pa2 wu2/pa3 pa4 pa5 pa6 pa7 port gpif master slave fifo figure 6. signals [+] feedback
cy7c68053 document # 001-06120 rev *j page 12 of 42 figure 7. cy7c68053 56-pin vf bga pin assignment - top view 12345678 a b c d e f g h 1a 2a 3a 4a 5a 6a 7a 8a 1b 2b 3b 4b 5b 6b 7b 8b 1c 2c 3c 4c 5c 6c 7c 8c 1d 2d 7d 8d 1e 2e 7e 8e 1f 2f 3f 4f 5f 6f 7f 8f 1g 2g 3g 4g 5g 6g 7g 8g 1h 2h 3h 4h 5h 6h 7h 8h [+] feedback
cy7c68053 document # 001-06120 rev *j page 13 of 42 4.1 cy7c68053 pin descriptions note 9. do not leave unused inputs floating. tie either high or low as appropriate. only pull outputs up or down to ensure signals at power up and in standby. do not drive any pins while the device is powered down. table 7. fx2lp18 pin descriptions [9] 56 vfbga name type default description 2d av cc power n/a analog vcc . connect this pin to 3.3 v power source. this signal provides power to the analog section of the chip. provide an appropriate bulk/bypass capacitance for this supply rail. 1d av cc power n/a analog vcc . connect this pin to 3.3 v power source. this signal provides power to the analog section of the chip. 2f agnd ground n/a analog ground . connect this pin to ground with as short a path as possible. 1f agnd ground n/a analog ground . connect to this pin ground with as short a path as possible. 1e dminus i/o/z z usb d? signal . connect this pin to the usb d? signal. 2e dplus i/o/z z usb d+ signal . connect this pin to the usb d+ signal. 8b reset# input n/a active low reset . this pin resets the entire chip. see reset and wakeup on page 6 for details. 1c xtalin input n/a crystal input . connect this signal to a 24 mhz parallel resonant, fundamental mode crystal and load capacitor to gnd. it is also correct to drive xtalin with an external 24 mhz square wave derived from another clock source. 2c xtalout output n/a crystal output . connect this signal to a 24 mhz parallel resonant, funda- mental mode crystal and load capacitor to gnd. if an external clock is used to drive xtalin, leave this pin open. 2b clkout o/z 12 mhz clkout. 12, 24, or 48 mhz clock, phase locked to the 24 mhz input clock. the 8051 defaults to 12 mhz operation. the 8051 may tri-state this output by setting cpucs.1 = 1. port a 8g pa0 or int0# i/o/z i (pa0) multiplexed pin whose function is selected by portacfg.0 pa0 is a bidirectional i/o port pin. int0# is the active low 8051 int0 interrupt input signal, which is either edge triggered (it0 = 1) or le vel triggered (it0 = 0). 6g pa1 or int1# i/o/z i (pa1) multiplexed pin whose function is selected by portacfg.1 pa1 is a bidirectional i/o port pin. int1# is the active low 8051 int1 interrupt input signal, which is either edge triggered (it1 = 1) or le vel triggered (it1 = 0). 8f pa2 or sloe i/o/z i (pa2) multiplexed pin whose function is se lected by two bits: ifconfig[1:0]. pa2 is a bidirectional i/o port pin. sloe is an input-only output enable with programmable polarity (fifopin- polar.4) for the slave fifo?s connected to fd[7:0] or fd[15:0]. 7f pa3 or wu2 i/o/z i (pa3) multiplexed pin whose function is selected by: wakeup.7 and oea.3 pa3 is a bidirectional i/o port pin. wu2 is an alternate source for usb wakeup, enabled by wu2en bit (wakeup.1) and polarity set by wu2pol (wakeup.4). if the 8051 is in suspend and wu2en = 1, a transition on th is pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. asserting this pin inhibits the chip from suspending, if wu2en = 1. [+] feedback
cy7c68053 document # 001-06120 rev *j page 14 of 42 6f pa4 or fifoadr0 i/o/z i (pa4) multiplexed pin whose function is selected by ifconfig[1:0]. pa4 is a bidirectional i/o port pin. fifoadr0 is an input-only address select for the slave fifos connected to fd[7:0] or fd[15:0]. 8c pa5 or fifoadr1 i/o/z i (pa5) multiplexed pin whose function is selected by ifconfig[1:0]. pa5 is a bidirectional i/o port pin. fifoadr1 is an input-only address select for the slave fifos connected to fd[7:0] or fd[15:0]. 7c pa6 or pktend i/o/z i (pa6) multiplexed pin whose function is se lected by the ifconfig[1:0] bits. pa6 is a bidirectional i/o port pin. pktend is an input that commits the fifo packet data to the endpoint and whose polarity is programmable using fifopinpolar.5. 6c pa7 or flagd or slcs# i/o/z i (pa7) multiplexed pin whose function is se lected by the ifconfig[1:0] and portacfg.7 bits. pa7 is a bidirectional i/o port pin. flagd is a programmable slave fifo output status flag signal. slcs# gates all other slave fifo enable/strobes port b 3h pb0 or fd[0] i/o/z i (pb0) multiplexed pin whose function is selected by ifconfig[1:0]. pb0 is a bidirectional i/o port pin. fd[0] is the bidirectional fifo/gpif data bus. 4f pb1 or fd[1] i/o/z i (pb1) multiplexed pin whose function is selected by ifconfig[1:0]. pb1 is a bidirectional i/o port pin. fd[1] is the bidirectional fifo/gpif data bus. 4h pb2 or fd[2] i/o/z i (pb2) multiplexed pin whose function is selected by ifconfig[1:0]. pb2 is a bidirectional i/o port pin. fd[2] is the bidirectional fifo/gpif data bus. 4g pb3 or fd[3] i/o/z i (pb3) multiplexed pin whose function is selected by ifconfig[1:0]. pb3 is a bidirectional i/o port pin. fd[3] is the bidirectional fifo/gpif data bus. 5h pb4 or fd[4] i/o/z i (pb4) multiplexed pin whose function is selected by ifconfig[1:0]. pb4 is a bidirectional i/o port pin. fd[4] is the bidirectional fifo/gpif data bus. 5g pb5 or fd[5] i/o/z i (pb5) multiplexed pin whose function is selected by ifconfig[1:0]. pb5 is a bidirectional i/o port pin. fd[5] is the bidirectional fifo/gpif data bus. 5f pb6 or fd[6] i/o/z i (pb6) multiplexed pin whose function is selected by ifconfig[1:0]. pb6 is a bidirectional i/o port pin. fd[6] is the bidirectional fifo/gpif data bus. 6h pb7 or fd[7] i/o/z i (pb7) multiplexed pin whose function is selected ifconfig[1:0]. pb7 is a bidirectional i/o port pin. fd[7] is the bidirectional fifo/gpif data bus. table 7. fx2lp18 pin descriptions (continued) [9] 56 vfbga name type default description [+] feedback
cy7c68053 document # 001-06120 rev *j page 15 of 42 port d 8a pd0 or fd[8] i/o/z i (pd0) multiplexed pin whose function is se lected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[8] is the bidirectional fifo/gpif data bus. 7a pd1 or fd[9] i/o/z i (pd1) multiplexed pin whose function is se lected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[9] is the bidirectional fifo/gpif data bus. 6b pd2 or fd[10] i/o/z i (pd2) multiplexed pin whose function is se lected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[10] is the bidirectional fifo/gpif data bus. 6a pd3 or fd[11] i/o/z i (pd3) multiplexed pin whose function is se lected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[11] is the bidirectional fifo/gpif data bus. 3b pd4 or fd[12] i/o/z i (pd4) multiplexed pin whose function is se lected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[12] is the bidirectional fifo/gpif data bus. 3a pd5 or fd[13] i/o/z i (pd5) multiplexed pin whose function is se lected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[13] is the bidirectional fifo/gpif data bus. 3c pd6 or fd[14] i/o/z i (pd6) multiplexed pin whose function is se lected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[14] is the bidirectional fifo/gpif data bus. 2a pd7 or fd[15] i/o/z i (pd7) multiplexed pin whose function is se lected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[15] is the bidirectional fifo/gpif data bus. 1a rdy0 or slrd input n/a multiplexed pin whose functi on is selected by ifconfig[1:0]. rdy0 is a gpif input signal. slrd is the input only read strobe with programmable polarity (fifopin- polar.3) for the slave fifos con nected to fd[7:0] or fd[15:0]. 1b rdy1 or slwr input n/a multiplexed pin whose functi on is selected by ifconfig[1:0]. rdy1 is a gpif input signal. slwr is the input only write strobe with programmable polarity (fifopin- polar.2) for the slave fifos con nected to fd[7:0] or fd[15:0]. 7h ctl0 or flaga o/z h multiplexed pin whose function is selected by ifconfig[1:0]. ctl0 is a gpif control output. flaga is a programmable slave fifo output status flag signal. defaults to programmable for the fifo selected by the fi foadr[1:0] pins. 7g ctl1 or flagb o/z h multiplexed pin whose function is selected by ifconfig[1:0]. ctl1 is a gpif control output. flagb is a programmable slave fifo output status flag signal. defaults to full for the fifo se lected by the fifoadr[1:0] pins. 8h ctl2 or flagc o/z h multiplexed pin whose function is selected ifconfig[1:0]. ctl2 is a gpif control output. flagc is a programmable slave fifo output status flag signal. defaults to empty for the fifo se lected by the fifo adr[1:0] pins. 2g ifclk i/o/z z interface clock, us ed to synchronous clock data into or out of the slave fifos. ifclk also serves as a timing reference for all slave fifo control signals and gpif. when internal clocking is used (ifconfig.7 = 1) the ifclk pin can be configured to output 30 or 48 mhz by bits ifconfig.5 and ifconfig.6. ifclk may be inverted, whether internally or externally sourced, by setting the bit ifconfig.4 =1. table 7. fx2lp18 pin descriptions (continued) [9] 56 vfbga name type default description [+] feedback
cy7c68053 document # 001-06120 rev *j page 16 of 42 7b wakeup input n/a usb wakeup . if the 8051 is in suspend, asserting this pin starts up the oscil- lator and interrupts the 8051 to allow it to exit the suspend mode. holding wakeup asserted inhibits the mobl-usb ? chip from suspending. this pin has programmable polarity (wakeup.4). 3f scl od z clock for the i 2 c interface. connect to v cc_io or v cc with a 2.2k?10k pull up resistor. (an i 2 c peripheral is required.) 3g sda od z data for the i 2 c interface. connect to v cc_io or v cc with a 2.2k?10k pull up resistor. (an i 2 c peripheral is required.) 5a v cc_io power n/a vcc . connect this pin to 1.8v to 3.3 v power source. provide the appropriate bulk and bypass capacitance for this supply rail. 5b v cc_io power n/a vcc . connect this pin to 1.8v to 3.3 v power source. 7e v cc_io power n/a vcc . connect this pin to 1.8 v to 3.3 v power source. 8e v cc_io power n/a vcc . connect this pin to 1.8v to 3.3 v power source. 5c v cc_d power n/a vcc . connect this pin to 1.8v power source. (supplies power to internal digital 1.8 v circuits.) provide the appropriate bulk and bypass capacitance for this supply rail. 1g v cc_a power n/a vcc . connect this pin to 1.8v power source. (supplies power to internal analog 1.8 v circuits.) 1h gnd ground n/a ground . 2h gnd ground n/a ground . 4a gnd ground n/a ground . 4b gnd ground n/a ground . 4c gnd ground n/a ground . 7d gnd ground n/a ground . 8d gnd ground n/a ground . table 7. fx2lp18 pin descriptions (continued) [9] 56 vfbga name type default description [+] feedback
cy7c68053 document # 001-06120 rev *j page 17 of 42 5. register summary fx2lp18 register bit definitions are described in the mobl-usb fx2lp18 trm in greater detail. table 8. fx2lp18 register summary hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access gpif waveform memories e400 128 wavedata gpif waveform descriptor 0, 1, 2, 3 data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e480 128 reserved general configuration e50d gpcr2 general purpose configura- tion register 2 reserved reserved reserved full_speed _only reserved reserved reserved reserved 00000000 r e600 1 cpucs cpu control and status 0 0 portcstb clkspd1 clkspd0 clkinv clkoe 8051res 00000010 rrbbbbbr e601 1 ifconfig interface configuration (ports, gpif, slave fifos) ifclksrc 3048mhz ifclkoe ifclkpol async gstate ifcfg1 ifcfg0 10000000 rw e602 1 pinflagsab [10] slave fifo flaga and flagb pin configuration flagb3 flagb2 flagb1 flagb0 flaga3 flaga2 flaga1 flaga0 00000000 rw e603 1 pinflagscd [10] slave fifo flagc and flagd pin configuration flagd3 flagd2 flagd1 flagd0 flagc3 flagc2 flagc1 flagc0 00000000 rw e604 1 fiforeset [10] restore fifos to default state nakall 0 0 0 ep3 ep2 ep1 ep0 xxxxxxxx w e605 1 breakpt breakpoint control 0 0 0 0 break bppulse bpen 0 00000000 rrrrbbbr e606 1 bpaddrh breakpoint address h a15 a14 a13 a12 a11 a10 a9 a8 xxxxxxxx rw e607 1 bpaddrl breakpoint address l a7 a6 a5 a4 a3 a2 a1 a0 xxxxxxxx rw e608 1 reserved reserved 0 0 0 0 0 0 0 0 00000000 rrrrrrbb e609 1 fifopinpolar [10] slave fifo interface pins polarity 0 0 pktend sloe slrd slwr ef ff 00000000 rrbbbbbb e60a 1 revid chip revision rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 reva 00000001 r e60b 1 revctl [10] chip revision control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 rrrrrrbb udma e60c 1 gpifholdamount mstb hold time (for udma) 0 0 0 0 0 0 holdtime1 holdtime0 00000000 rrrrrrbb 3 reserved endpoint configuration e610 1 ep1outcfg endpoint 1-out configuration valid 0 type1 type0 0 0 0 0 10100000 brbbrrrr e611 1 ep1incfg endpoint 1-in configuration valid 0 type1 type0 0 0 0 0 10100000 brbbrrrr e612 1 ep2cfg endpoint 2 configuration valid dir type1 type0 size 0 buf1 buf0 10100010 bbbbbrbb e613 1 ep4cfg endpoint 4 configuration valid dir type1 type0 0 0 0 0 10100000 bbbbrrrr e614 1 ep6cfg endpoint 6 configuration valid dir type1 type0 size 0 buf1 buf0 11100010 bbbbbrbb e615 1 ep8cfg endpoint 8 configuration valid dir type1 type0 0 0 0 0 11100000 bbbbrrrr 2 reserved e618 1 ep2fifocfg [10] endpoint 2/slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e619 1 ep4fifocfg [10] endpoint 4/slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e61a 1 ep6fifocfg [10] endpoint 6/slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e61b 1 ep8fifocfg [10] endpoint 8/slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e61c 4 reserved e620 1 ep2autoinlenh [10 endpoint 2 autoin packet length h 0 0 0 0 0 pl10 pl9 pl8 00000010 rrrrrbbb e621 1 ep2autoinlenl [10] endpoint 2 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e622 1 ep4autoinlenh [10 ] endpoint 4 autoin packet length h 0 0 0 0 0 0 pl9 pl8 00000010 rrrrrrbb e623 1 ep4autoinlenl [10] endpoint 4 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e624 1 ep6autoinlenh [10 ] endpoint 6 autoin packet length h 0 0 0 0 0 pl10 pl9 pl8 00000010 rrrrrbbb e625 1 ep6autoinlenl [10] endpoint 6 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e626 1 ep8autoinlenh [10 ] endpoint 8 autoin packet length h 0 0 0 0 0 0 pl9 pl8 00000010 rrrrrrbb e627 1 ep8autoinlenl [10] endpoint 8 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e628 1 ecccfg ecc configuration 0 0 0 0 0 0 0 eccm 00000000 rrrrrrrb e629 1 eccreset ecc reset x x x x x x x x 00000000 w e62a 1 ecc1b0 ecc1 byte 0 address line15 line14 line13 line12 line11 line10 line9 line8 00000000 r e62b 1 ecc1b1 ecc1 byte 1 address line7 line6 line5 line4 line3 line2 line1 line0 00000000 r note 10. read and writes to these registers may require synchronization delay, see mobl-usb fx2lp18 technical reference manual for ?synchronization delay.? [+] feedback
cy7c68053 document # 001-06120 rev *j page 18 of 42 e62c 1 ecc1b2 ecc1 byte 2 address col5 col4 col3 col2 col1 col0 line17 line16 00000000 r e62d 1 ecc2b0 ecc2 byte 0 address line15 line14 line13 line12 line11 line10 line9 line8 00000000 r e62e 1 ecc2b1 ecc2 byte 1 address line7 line6 line5 line4 line3 line2 line1 line0 00000000 r e62f 1 ecc2b2 ecc2 byte 2 address col5 col4 col3 col2 col1 col0 0 0 00000000 r e630 h.s. 1 ep2fifopfh [10] endpoint 2/slave fifo programmable flag h decis pktstat in:pkts[2] out:pfc12 in:pkts[1] out:pfc11 in:pkts[0] out:pfc10 0 pfc9 pfc8 10001000 bbbbbrbb e630 f. s . 1 ep2fifopfh [10] endpoint 2/slave fifo programmable flag h decis pktstat out:pfc12 out:pfc11 out:pfc10 0 pfc9 in:pkts[2] out:pfc8 10001000 bbbbbrbb e631 h.s. 1 ep2fifopfl [10] endpoint 2/slave fifo programmable flag l pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e631 f. s 1 ep2fifopfl [10] endpoint 2/slave fifo programmable flag l in:pkts[1] out:pfc7 in:pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e632 h.s. 1 ep4fifopfh [10] endpoint 4/slave fifo programmable flag h decis pktstat 0 in: pkts[1] out:pfc10 in: pkts[0] out:pfc9 0 0 pfc8 10001000 bbrbbrrb e632 f. s 1 ep4fifopfh [10] endpoint 4/slave fifo programmable flag h decis pktstat 0 out:pfc10 out:pfc9 0 0 pfc8 10001000 bbrbbrrb e633 h.s. 1 ep4fifopfl [10] endpoint 4/slave fifo programmable flag l pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e633 f. s 1 ep4fifopfl [10] endpoint 4/slave fifo programmable flag l in: pkts[1] out:pfc7 in: pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e634 h.s. 1 ep6fifopfh [10] endpoint 6/slave fifo programmable flag h decis pktstat in:pkts[2] out:pfc12 in:pkts[1] out:pfc11 in:pkts[0] out:pfc10 0 pfc9 pfc8 00001000 bbbbbrbb e634 f. s 1 ep6fifopfh [10] endpoint 6/slave fifo programmable flag h decis pktstat out:pfc12 out:pfc11 out:pfc10 0 pfc9 in:pkts[2] out:pfc8 00001000 bbbbbrbb e635 h.s. 1 ep6fifopfl [10] endpoint 6/slave fifo programmable flag l pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e635 f. s 1 ep6fifopfl [10] endpoint 6/slave fifo programmable flag l in:pkts[1] out:pfc7 in:pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e636 h.s. 1 ep8fifopfh [10] endpoint 8/slave fifo programmable flag h decis pktstat 0 in: pkts[1] out:pfc10 in: pkts[0] out:pfc9 0 0 pfc8 00001000 bbrbbrrb e636 f. s 1 ep8fifopfh [10] endpoint 8/slave fifo programmable flag h decis pktstat 0 out:pfc10 out:pfc9 0 0 pfc8 00001000 bbrbbrrb e637 h.s. 1 ep8fifopfl [10] endpoint 8/slave fifo programmable flag l pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e637 f. s 1 ep8fifopfl [10] endpoint 8/slave fifo programmable flag l in: pkts[1] out:pfc7 in: pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw 8 reserved e640 1 ep2isoinpkts ep2 (if iso) in packets per frame (1-3) aadj 0 0 0 0 0 inppf1 inppf0 00000001 brrrrrbb e641 1 ep4isoinpkts ep4 (if iso) in packets per frame (1-3) aadj 0 0 0 0 0 inppf1 inppf0 00000001 brrrrrrr e642 1 ep6isoinpkts ep6 (if iso) in packets per frame (1-3) aadj 0 0 0 0 0 inppf1 inppf0 00000001 brrrrrbb e643 1 ep8isoinpkts ep8 (if iso) in packets per frame (1-3) aadj 0 0 0 0 0 inppf1 inppf0 00000001 brrrrrrr e644 4 reserved e648 1 inpktend [10] force in packet end skip 0 0 0 ep3 ep2 ep1 ep0 xxxxxxxx w e649 7 outpktend [10] force out packet end skip 0 0 0 ep3 ep2 ep1 ep0 xxxxxxxx w interrupts e650 1 ep2fifoie [10] endpoint 2 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e651 1 ep2fifoirq [10,11] endpoint 2 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000000 rrrrrbbb e652 1 ep4fifoie [10] endpoint 4 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e653 1 ep4fifoirq [10,11] endpoint 4 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000000 rrrrrbbb e654 1 ep6fifoie [10] endpoint 6 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e655 1 ep6fifoirq [10,11] endpoint 6 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000000 rrrrrbbb e656 1 ep8fifoie [10] endpoint 8 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e657 1 ep8fifoirq [10,11] endpoint 8 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000000 rrrrrbbb e658 1 ibnie in-bulk-nak interrupt enable 0 0 ep8 ep6 ep4 ep2 ep1 ep0 00000000 rw e659 1 ibnirq [11] in-bulk-nak interrupt request 0 0 ep8 ep6 ep4 ep2 ep1 ep0 00xxxxxx rrbbbbbb e65a 1 nakie endpoint ping-nak/ibn interrupt enable ep8 ep6 ep4 ep2 ep1 ep0 0 ibn 00000000 rw e65b 1 nakirq [11] endpoint ping-nak/ibn interrupt request ep8 ep6 ep4 ep2 ep1 ep0 0 ibn xxxxxx0x bbbbbbrb e65c 1 usbie usb interrupt enables 0 ep0ack hsgrant ures susp sutok sof sudav 00000000 rw e65d 1 usbirq [11] usb interrupt requests 0 ep0ack hsgrant ures susp sutok sof sudav 0xxxxxxx rbbbbbbb table 8. fx2lp18 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 11. the register can only be reset, it cannot be set. [+] feedback
cy7c68053 document # 001-06120 rev *j page 19 of 42 e65e 1 epie endpoint interrupt enables ep8 ep6 ep4 ep2 ep1out ep1in ep0out ep0in 00000000 rw e65f 1 epirq [11] endpoint interrupt requests ep8 ep6 ep4 ep2 ep1out ep1in ep0out ep0in 0 rw e660 1 gpifie [10] gpif interrupt enable 0 0 0 0 0 0 gpifwf gpifdone 00000000 rw e661 1 gpifirq [10] gpif interrupt request 0 0 0 0 0 0 gpifwf gpifdone 000000xx rw e662 1 usberrie usb error interrupt enables isoep8 isoep6 isoep4 isoep2 0 0 0 errlimit 00000000 rw e663 1 usberrirq [11] usb error interrupt requests isoep8 isoep6 isoep4 isoep2 0 0 0 errlimit 0000000x bbbbrrrb e664 1 errcntlim usb error counter and limit ec3 ec2 ec1 ec0 limit3 limit2 limit1 limit0 xxxx0100 rrrrbbbb e665 1 clrerrcnt clear error counter ec3:0 x x x x x x x x xxxxxxxx w e666 1 int2ivec interrupt 2 (usb) autovector 0 i2v4 i2v3 i2v2 i2v1 i2v0 0 0 00000000 r e667 1 reserved 1 0 0 0 0 0 0 0 10000000 r e668 1 intset-up interrupt 2 and 4 setup 0 0 0 0 av2en 0 reserved av4en 00000000 rw e669 7 reserved input/output e670 1 portacfg i/o porta alternate configuration flagd slcs 0 0 0 0 int1 int0 00000000 rw e671 1 portccfg i/o portc alternate configuration gpifa7 gpifa6 gpifa5 gpifa4 gpifa3 gpifa2 gpifa1 gpifa0 00000000 rw e672 1 portecfg i/o porte alternate configuration gpifa8 t2ex int6 rxd1out rxd0out t2out t1out t0out 00000000 rw e673 4 reserved e677 1 reserved e678 1 i2cs i2c bus control and status start stop lastrd id1 id0 berr ack done 000xx000 bbbrrrrr e679 1 i2dat i2c bus data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e67a 1 i2ctl i2c bus control 0 0 0 0 0 0 stopie 400khz 00000000 rw e67b 1 xautodat1 autoptr1 movx access, when aptren = 1 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e67c 1 xautodat2 autoptr2 movx access, when aptren = 1 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw udma crc e67d 1 udmacrch [10] udma crc msb crc15 crc14 crc13 crc12 crc11 crc10 crc9 crc8 01001010 rw e67e 1 udmacrcl [10] udma crc lsb crc7 crc6 crc5 crc4 crc3 crc2 crc1 crc0 10111010 rw e67f 1 udmacrc- qualifier udma crc qualifier qenable 0 0 0 qstate qsignal2 qsignal1 qsignal0 00000000 brrrbbbb usb control e680 1 usbcs usb control and status hsm 0 0 0 discon nosynsof renum sigrsume x0000000 rrrrbbbb e681 1 suspend put chip into suspend x x x x x x x x xxxxxxxx w e682 1 wakeupcs wakeup control and status wu2 wu wu2pol wupol 0 dpen wu2en wuen xx000101 bbbbrbbb e683 1 togctl toggle control q s r i/o ep3 ep2 ep1 ep0 x0000000 rrrbbbbb e684 1 usbframeh usb frame count h 0 0 0 0 0 fc10 fc9 fc8 00000xxx r e685 1 usbframel usb frame count l fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 xxxxxxxx r e686 1 microframe microframe count, 0-7 0 0 0 0 0 mf2 mf1 mf0 00000xxx r e687 1 fnaddr usb function address 0 fa6 fa5 fa4 fa3 fa2 fa1 fa0 0xxxxxxx r e688 2 reserved endpoints e68a 1 ep0bch [10] endpoint 0 byte count h (bc15) (bc14) (bc13) (bc12) (bc11) (bc10) (bc9) (bc8) xxxxxxxx rw e68b 1 ep0bcl [10] endpoint 0 byte count l (bc7) bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e68c 1 reserved e68d 1 ep1outbc endpoint 1 out byte count 0 bc6 bc5 bc4 bc3 bc2 bc1 bc0 0xxxxxxx rw e68e 1 reserved e68f 1 ep1inbc endpoint 1 in byte count 0 bc6 bc5 bc4 bc3 bc2 bc1 bc0 0xxxxxxx rw e690 1 ep2bch [10] endpoint 2 byte count h 0 0 0 0 0 bc10 bc9 bc8 00000xxx rw e691 1 ep2bcl [10] endpoint 2 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e692 2 reserved e694 1 ep4bch [10] endpoint 4 byte count h 0 0 0 0 0 0 bc9 bc8 000000xx rw e695 1 ep4bcl [10] endpoint 4 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e696 2 reserved e698 1 ep6bch [10] endpoint 6 byte count h 0 0 0 0 0 bc10 bc9 bc8 00000xxx rw e699 1 ep6bcl [10] endpoint 6 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e69a 2 reserved e69c 1 ep8bch [10] endpoint 8 byte count h 0 0 0 0 0 0 bc9 bc8 000000xx rw e69d 1 ep8bcl [10] endpoint 8 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e69e 2 reserved e6a0 1 ep0cs endpoint 0 control and status hsnak 0 0 0 0 0 busy stall 10000000 bbbbbbrb e6a1 1 ep1outcs endpoint 1 out control and status 0 0 0 0 0 0 busy stall 00000000 bbbbbbrb table 8. fx2lp18 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access [+] feedback
cy7c68053 document # 001-06120 rev *j page 20 of 42 e6a2 1 ep1incs endpoint 1 in control and status 0 0 0 0 0 0 busy stall 00000000 bbbbbbrb e6a3 1 ep2cs endpoint 2 control and status 0 npak2 npak1 npak0 full empty 0 stall 00101000 rrrrrrrb e6a4 1 ep4cs endpoint 4 control and status 0 0 npak1 npak0 full empty 0 stall 00101000 rrrrrrrb e6a5 1 ep6cs endpoint 6 control and status 0 npak2 npak1 npak0 full empty 0 stall 00000100 rrrrrrrb e6a6 1 ep8cs endpoint 8 control and status 0 0 npak1 npak0 full empty 0 stall 00000100 rrrrrrrb e6a7 1 ep2fifoflgs endpoint 2 slave fifo flags 0 0 0 0 0 pf ef ff 00000010 r e6a8 1 ep4fifoflgs endpoint 4 slave fifo flags 0 0 0 0 0 pf ef ff 00000010 r e6a9 1 ep6fifoflgs endpoint 6 slave fifo flags 0 0 0 0 0 pf ef ff 00000110 r e6aa 1 ep8fifoflgs endpoint 8 slave fifo flags 0 0 0 0 0 pf ef ff 00000110 r e6ab 1 ep2fifobch endpoint 2 slave fifo total byte count h 0 0 0 bc12 bc11 bc10 bc9 bc8 00000000 r e6ac 1 ep2fifobcl endpoint 2 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6ad 1 ep4fifobch endpoint 4 slave fifo total byte count h 0 0 0 0 0 bc10 bc9 bc8 00000000 r e6ae 1 ep4fifobcl endpoint 4 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6af 1 ep6fifobch endpoint 6 slave fifo total byte count h 0 0 0 0 bc11 bc10 bc9 bc8 00000000 r e6b0 1 ep6fifobcl endpoint 6 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6b1 1 ep8fifobch endpoint 8 slave fifo total byte count h 0 0 0 0 0 bc10 bc9 bc8 00000000 r e6b2 1 ep8fifobcl endpoint 8 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6b3 1 sudptrh setup data pointer high address byte a15 a14 a13 a12 a11 a10 a9 a8 xxxxxxxx rw e6b4 1 sudptrl setup data pointer low address byte a7 a6 a5 a4 a3 a2 a1 0 xxxxxxx0 bbbbbbbr e6b5 1 sudptrctl setup data pointer auto mode 0 0 0 0 0 0 0 sdpauto 00000001 rw 2 reserved e6b8 8 set-updat 8 bytes of setup data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx r set-updat[0] = bmrequesttype set-updat[1] = bmrequest set-updat[2:3] = wvalue set-updat[4:5] = windex set-updat[6:7] = wlength gpif e6c0 1 gpifwfselect waveform selector singlewr1 singlewr0 singlerd1 singlerd0 fifowr1 fifowr0 fiford1 fiford0 11100100 rw e6c1 1 gpifidlecs gpif done, gpif idle drive mode done 0 0 0 0 0 0 idledrv 10000000 rw e6c2 1 gpifidlectl inactive bus, ctl states 0 0 0 0 0 ctl2 ctl1 ctl0 11111111 rw e6c3 1 gpifctlcfg ctl drive type trictl 0 0 0 0 ctl2 ctl1 ctl0 00000000 rw e6c4 1 reserved 00000000 e6c5 1 reserved 00000000 flowstate e6c6 1 flowstate flowstate enable and selector fse 0 0 0 0 fs2 fs1 fs0 00000000 brrrrbbb e6c7 1 flowlogic flowstate logic lfunc1 lfunc0 terma2 terma1 terma0 termb2 termb1 termb0 00000000 rw e6c8 1 floweq0ctl ctl-pin states in flow state (when logic = 0) ctl0e3 ctl0e2 ctl0e1 ctl0e0 0 ctl2 ctl1 ctl0 00000000 rw e6c9 1 floweq1ctl ctl-pin states in flow state (when logic = 1) ctl0e3 ctl0e2 ctl0e1 ctl0e0 0 ctl2 ctl1 ctl0 00000000 rw e6ca 1 flowholdoff holdoff configuration hoperiod3 hoperiod2 hoperiod1 hoperiod0 hostate hoctl2 hoctl1 hoctl0 00010010 rw e6cb 1 flowstb flowstate strobe configuration slave rdyasync ctltogl sustain 0 mstb2 mstb1 mstb0 00100000 rw e6cc 1 flowstbedge flowstate rising/falling edge configuration 0 0 0 0 0 0 falling rising 00000001 rrrrrrbb e6cd 1 flowstbperiod master strobe half period d7 d6 d5 d4 d3 d2 d1 d0 00000010 rw e6ce 1 gpiftcb3 [10] gpif transaction count byte 3 tc31 tc30 tc29 tc28 tc27 tc26 tc25 tc24 00000000 rw e6cf 1 gpiftcb2 [10] gpif transaction count byte 2 tc23 tc22 tc21 tc20 tc19 tc18 tc17 tc16 00000000 rw e6d0 1 gpiftcb1 [10] gpif transaction count byte 1 tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 00000000 rw e6d1 1 gpiftcb0 [10] gpif transaction count byte 0 tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 00000001 rw 2 reserved 00000000 rw reserved table 8. fx2lp18 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access [+] feedback
cy7c68053 document # 001-06120 rev *j page 21 of 42 reserved e6d2 1 ep2gpifflgsel [10] endpoint 2 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6d3 1 ep2gpifpfstop endpoint 2 gpif stop trans- action on program flag 0 0 0 0 0 0 0 fifo2flag 00000000 rw e6d4 1 ep2gpiftrig [10] endpoint 2 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved reserved reserved e6da 1 ep4gpifflgsel [10] endpoint 4 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6db 1 ep4gpifpfstop endpoint 4 gpif stop trans- action on gpif flag 0 0 0 0 0 0 0 fifo4flag 00000000 rw e6dc 1 ep4gpiftrig [10] endpoint 4 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved reserved reserved e6e2 1 ep6gpifflgsel [10] endpoint 6 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6e3 1 ep6gpifpfstop endpoint 6 gpif stop trans- action on program flag 0 0 0 0 0 0 0 fifo6flag 00000000 rw e6e4 1 ep6gpiftrig [10] endpoint 6 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved reserved reserved e6ea 1 ep8gpifflgsel [10] endpoint 8 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6eb 1 ep8gpifpfstop endpoint 8 gpif stop trans- action on program flag 0 0 0 0 0 0 0 fifo8flag 00000000 rw e6ec 1 ep8gpiftrig [10] endpoint 8 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved e6f0 1 xgpifsgldath gpif data h (16-bit mode only) d15 d14 d13 d12 d11 d10 d9 d8 xxxxxxxx rw e6f1 1 xgpifsgldatlx read/write gpif data l and trigger transaction d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e6f2 1 xgpifsgldatl- nox read gpif data l, no trans- action trigger d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx r e6f3 1 gpifreadycfg internal rdy, sync/async, rdy pin states intrdy sas tcxrdy5 0 0 0 0 0 00000000 bbbrrrrr e6f4 1 gpifreadystat gpif ready status 0 0 0 0 0 0 rdy1 rdy0 00xxxxxx r e6f5 1 gpifabort abort gpif waveforms x x x x x x x x xxxxxxxx w e6f6 2 reserved endpoint buffers e740 64 ep0buf ep0-in/-out buffer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e780 64 ep10utbuf ep1-out buffer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e7c0 64 ep1inbuf ep1-in buffer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e800 2048 reserved rw f000 1024 ep2fifobuf 512/1024-byte ep 2/slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw f400 512 ep4fifobuf 512 byte ep 4/slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw f600 512 reserved f800 1024 ep6fifobuf 512/1024-byte ep 6/slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw fc00 512 ep8fifobuf 512 byte ep 8/slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw fe00 512 reserved xxxx i2c configuration byte 0 discon 0 0 0 0 0 400khz xxxxxxxx [12] n/a table 8. fx2lp18 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 12. if no eeprom is detected by the sie then the default is 00000000. [+] feedback
cy7c68053 document # 001-06120 rev *j page 22 of 42 special function registers (sfrs) 80 1 ioa [13] port a (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw 81 1 sp stack pointer d7 d6 d5 d4 d3 d2 d1 d0 00000111 rw 82 1 dpl0 data pointer 0 l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 83 1 dph0 data pointer 0 h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 84 1 dpl1 [13] data pointer 1 l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 85 1 dph1 [13] data pointer 1 h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 86 1 dps [13] data pointer 0/1 select 0 0 0 0 0 0 0 sel 00000000 rw 87 1 pcon power control smod0 x 1 1 x x x idle 00110000 rw 88 1 tcon timer/counter control (bit addressable) tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000 rw 89 1 tmod timer/counter mode control gate ct m1 m0 gate ct m1 m0 00000000 rw 8a 1 tl0 timer 0 reload l d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw 8b 1 tl1 timer 1 reload l d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw 8c 1 th0 timer 0 reload h d15 d14 d13 d12 d11 d10 d9 d8 00000000 rw 8d 1 th1 timer 1 reload h d15 d14 d13 d12 d11 d10 d9 d8 00000000 rw 8e 1 ckcon [13] clock control x x t2m t1m t0m md2 md1 md0 00000001 rw 8f 1 reserved 90 1 iob [13] port b (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw 91 1 exif [13] external interrupt flags ie5 ie4 i2cint usbnt 1 0 0 0 00001000 rw 92 1 mpage [13] upper address byte of movx using @r0/@r1 a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 93 5 reserved 98 1 scon0 serial port 0 control (bit addressable) sm0_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 00000000 rw 99 1 sbuf0 serial port 0 data buffer d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw 9a 1 autoptrh1 [13] autopointer 1 address h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 9b 1 autoptrl1 [13] autopointer 1 address l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 9c 1 reserved 9d 1 autoptrh2 [13] autopointer 2 address h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 9e 1 autoptrl2 [13] autopointer 2 address l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 9f 1 reserved a0 1 ioc [13] port c (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw a1 1 int2clr [13] interrupt 2 clear x x x x x x x x xxxxxxxx w a2 1 reserved x x x x x x x x xxxxxxxx w a3 5 reserved a8 1 ie interrupt enable (bit addressable) ea es1 et2 es0 et1 ex1 et0 ex0 00000000 rw a9 1 reserved aa 1 ep2468stat [13] endpoint 2,4,6,8 status flags ep8f ep8e ep6f ep6e ep4f ep4e ep2f ep2e 01011010 r ab 1 ep24fifoflgs [13] endpoint 2,4 slave fifo status flags 0 ep4pf ep4ef ep4ff 0 ep2pf ep2ef ep2ff 00100010 r ac 1 ep68fifoflgs [13] endpoint 6,8 slave fifo status flags 0 ep8pf ep8ef ep8ff 0 ep6pf ep6ef ep6ff 01100110 r ad 2 reserved af 1 autoptrsetup [13] autopointer 1 and 2 setup 0 0 0 0 0 aptr2inc aptr1inc aptren 00000110 rw b0 1 iod [13] port d (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw b1 1 ioe [13] port e (not bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw b2 1 oea [13] port a output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b3 1 oeb [13] port b output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b4 1 oec [13] port c output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b5 1 oed [13] port d output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b6 1 oee [13] port e output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b7 1 reserved b8 1 ip interrupt priority (bit address- able) 1 ps1 pt2 ps0 pt1 px1 pt0 px0 10000000 rw b9 1 reserved ba 1 ep01stat [13] endpoint 0 and 1 status 0 0 0 0 0 ep1inbsy ep1outbsy ep0bsy 00000000 r bb 1 gpiftrig [13, 10] endpoint 2,4,6,8 gpif slave fifo trigger done 0 0 0 0 rw ep1 ep0 10000xxx brrrrbbb bc 1 reserved bd 1 gpifsgldath [13] gpif data h (16-bit mode only) d15 d14 d13 d12 d11 d10 d9 d8 xxxxxxxx rw be 1 gpifsgldatlx [13] gpif data l w/trigger d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw bf 1 gpifsgldatl- nox [13] gpif data l w/no trigger d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx r table 8. fx2lp18 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 13. sfrs not part of the standard 8051 architecture. [+] feedback
cy7c68053 document # 001-06120 rev *j page 23 of 42 c0 1 scon1 [13] serial port 1 control (bit addressable) sm0_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 00000000 rw c1 1 sbuf1 [13] serial port 1 data buffer d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw c2 6 reserved c8 1 t2con timer/counter 2 control (bit addressable) tf2 exf2 rclk tclk exen2 tr2 ct2 cprl2 00000000 rw c9 1 reserved ca 1 rcap2l capture for timer 2, auto-reload, up counter d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw cb 1 rcap2h capture for timer 2, auto-reload, up counter d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw cc 1 tl2 timer 2 reload l d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw cd 1 th2 timer 2 reload h d15 d14 d13 d12 d11 d10 d9 d8 00000000 rw ce 2 reserved d0 1 psw program status word (bit ad- dressable) cy ac f0 rs1 rs0 ov f1 p 00000000 rw d1 7 reserved d8 1 eicon [13] external interrupt control smod1 1 eresi resi int6 0 0 0 01000000 rw d9 7 reserved e0 1 acc accumulator (bit address- able) d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw e1 7 reserved e8 1 eie [13] external interrupt enables 1 1 1 ex6 ex5 ex4 ei2c eusb 11100000 rw e9 7 reserved f0 1 b b (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw f1 7 reserved f8 1 eip [13] external interrupt priority control 1 1 1 px6 px5 px4 pi2c pusb 11100000 rw f9 7 reserved table 8. fx2lp18 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access ledgend r = all bits read only w = all bits write only r = read-only bit w = write-only bit b = both read/write bit [+] feedback
cy7c68053 document # 001-06120 rev *j page 24 of 42 6. absolute maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature... ............... .............. ... ?65c to +150c ambient temperature with power supplied industrial ....................................................... ?40c to +85c supply voltage to ground potential for 3.3 v power domain ...............................?0.5 v to +4.0 v for 1.8 v power domain ...............................?0.5 v to +2.0 v dc input voltage to any input pin for pins under 3.3 v power domain ......................... 3.6 v [14] for pins under 1.8 v to 3.3 v power domain (gpios)1.89 v to 3.6 v [14] (the gpios are not over voltage tolerant, except the scl and sda pins, which are 3.3 v tolerant) dc voltage applied to outputs in high z state ?0.5 v to vcc +0.5 v maximum power dissipation from avcc supply ...................................................... 90 mw from i/o supply .......................................................... 36 mw from core supply........................................................ 95 mw static discharge voltage............................................ >2000 v (i2c scl and sda pins only .................................. >1500 v) maximum output current, per i/o port.......................... 10 ma 7. operating conditions t a (ambient temperature under bias) industrial ..................................................... ?40 c to +85 c supply voltage 3.3 v power supply ..........................................3.0 v to 3.6 v 1.8 v power supply .......................................1.71 v to1.89 v ground voltage................................................................. 0 v f osc (oscillator or crystal frequency).... 24 mhz 100 ppm ................................................................... parallel resonant ............. .............. .............. .............. ........... 500 w drive level ............. .............. .............. .............. ..... load capacitors 12 pf 8. dc characteristics note 14. do not power i/o when chip power is off. table 9. dc characteristics parameter description conditions min typ max unit av cc 3.3 v supply (to oscillator and phy) 3.00 3.3 3.60 v v cc_io 1.8 v to 3.3 v supply (to i/o) 1.71 1.8 3.60 v v cc_a 1.8 v supply to analog core 1.71 1.8 1.89 v v cc_d 1.8 v supply to digital core 1.71 1.8 1.89 v v ih input high voltage 0.6*v cc_io v cc_io+10% v v il input low voltage 0 0.3*v cc_io v v ih_x crystal input high voltage 2.0 3.60 v v il_x crystal input low voltage ?0.5 0.8 v hysteresis 50 mv i i input leakage current 0< v in < v cc_io 10 a v oh output voltage high i out = 4 ma v cc_io ? 0.4 v v ol output low voltage i out = ?4 ma 0.4 v i oh output current high 4ma i ol output current low 4ma c in input pin capacitance except d+/d? 10 pf d+/d? 15 pf i susp suspend current connected 220 380 [15] a disconnected 20 150 [15] a note 15. measured at maximum v cc , 25c. [+] feedback
cy7c68053 document # 001-06120 rev *j page 25 of 42 9. ac electrical characteristics 9.1 usb transceiver usb 2.0-compliant in full and high speed modes. 9.2 gpif synchronous signals i cc_avcc supply current (av cc ) 8051 running, connected to usb hs 15 25 ma 8051 running, connected to usb fs 10 20 ma i cc_io supply current (v cc_io ) 8051 running, connected to usb hs 3 10 ma 8051 running, connected to usb fs 1 5 ma i cc_core supply current (v cc_core ) 8051 running, connected to usb hs 32 50 ma 8051 running, connected to usb fs 24 40 ma t reset reset time after valid power v cc min = 3.0 v 5.0 ms pin reset after powered on 200 s table 9. dc characteristics parameter description conditions min typ max unit data(output) t xgd ifclk rdy x data(input) valid t sry t ryh t ifclk t sgd ctl x t xctl t dah n n+1 gpifadr[8:0] t sga figure 8. gpif synchronous signals timing diagram [16] table 10. gpif synchronous signals para meters with internally sourced ifclk [16,17] parameter description min max unit t ifclk ifclk period 20.83 ns t sry rdy x to clock setup time 8.9 ns t ryh clock to rdy x 0ns t sgd gpif data to clock setup time 9.2 ns t dah gpif data hold time 0 ns t xgd clock to gpif data output propagation delay 11 ns t xctl clock to ctl x output propagation delay 6.7 ns [+] feedback
cy7c68053 document # 001-06120 rev *j page 26 of 42 8 9.3 slave fifo synchronous read notes 16. dashed lines denote signals with programmable polarity. 17. gpif asynchronous rdy x signals have a minimum setup time of 50 ns when using internal 48 mhz ifclk. 18. ifclk must not exceed 48 mhz. table 11. gpif synchronous signals para meters with externally sourced ifclk [17] parameter description min max unit t ifclk ifclk period [18] 20.83 200 ns t sry rdy x to clock setup time 2.9 ns t ryh clock to rdy x 3.7 ns t sgd gpif data to clock setup time 3.2 ns t dah gpif data hold time 4.5 ns t xgd clock to gpif data output propagation delay 15 ns t xctl clock to ctl x output propagation delay 13.06 ns ifclk slrd flags sloe t srd t rdh t oeon t xfd t xflg data t ifclk n+1 t oeoff n figure 9. slave fifo synchronous read timing diagram [16] table 12. slave fifo synchronous read parameters with internally sourced ifclk [17] parameter description min max unit t ifclk ifclk period 20.83 ns t srd slrd to clock setup time 18.7 ns t rdh clock to slrd hold time 0 ns t oeon sloe turn-on to fifo data valid 10.5 ns t oeoff sloe turn-off to fifo data hold 2.15 10.5 ns t xflg clock to flags output propagation delay 9.5 ns t xfd clock to fifo data output propagation delay 11 ns [+] feedback
cy7c68053 document # 001-06120 rev *j page 27 of 42 9.4 slave fifo asynchronous read table 13. slave fifo synchronous read parameters with externally sourced ifclk [17] parameter description min max unit t ifclk ifclk period 20.83 200 ns t srd slrd to clock setup time 12.7 ns t rdh clock to slrd hold time 3.7 ns t oeon sloe turn-on to fifo data valid 10.5 ns t oeoff sloe turn-off to fifo data hold 2.15 10.5 ns t xflg clock to flags output propagation delay 13.5 ns t xfd clock to fifo data output propagation delay 17.31 ns slrd flags t rdpwl t rdpwh sloe t xflg t xfd data t oeon t oeoff n+1 n figure 10. slave fifo asynchronous read timing diagram [16] note 19. slave fifo asynchronous parameter values use internal ifclk setting at 48 mhz. table 14. slave fifo asynchronous read parameters [19] parameter description min max unit t rdpwl slrd pulse width low 50 ns t rdpwh slrd pulse width high 50 ns t xflg slrd to flags output propagation delay 70 ns t xfd slrd to fifo data output propagation delay 15 ns t oeon sloe turn-on to fifo data valid 10.5 ns t oeoff sloe turn-off to fifo data hold 2.15 10.5 ns [+] feedback
cy7c68053 document # 001-06120 rev *j page 28 of 42 9.5 slave fifo synchronous write z z t sfd t fdh data ifclk slwr flags t wrh t xflg t ifclk t swr n figure 11. slave fifo synchronous write timing diagram [16] table 15. slave fifo synchronous write parameters with internally sourced ifclk [17] parameter description min max unit t ifclk ifclk period 20.83 ns t swr slwr to clock setup time 18.1 ns t wrh clock to slwr hold time 0 ns t sfd fifo data to clock setup time 10.64 ns t fdh clock to fifo data hold time 0 ns t xflg clock to flags output propagation time 9.5 ns table 16. slave fifo synchronous write parameters with externally sourced ifclk [10] parameter description min max unit t ifclk ifclk period 20.83 200 ns t swr slwr to clock setup time 12.1 ns t wrh clock to slwr hold time 3.6 ns t sfd fifo data to clock setup time 3.2 ns t fdh clock to fifo data hold time 4.5 ns t xflg clock to flags output propagation time 13.5 ns [+] feedback
cy7c68053 document # 001-06120 rev *j page 29 of 42 9.6 slave fifo asynchronous write 9.7 slave fifo synchronous packet end strobe data t sfd t fdh flags t xfd t wrpwh t wrpwl figure 12. slave fifo asynchronous write timing diagram [16] slwr table 17. slave fifo asynchronous write parameters with internally sourced ifclk [19] parameter description min max unit t wrpwl slwr pulse low 50 ns t wrpwh slwr pulse high 50 ns t sfd slwr to fifo data setup time 10 ns t fdh fifo data to slwr hold time 10 ns t xfd slwr to flags output propagation delay 70 ns flags t xflg ifclk pktend t spe t peh figure 13. slave fifo synchronous packet end strobe timing diagram [16] table 18. slave fifo synchronous packet end stro be parameters with in ternally sourced ifclk [10] parameter description min max unit t ifclk ifclk period 20.83 ns t spe pktend to clock setup time 14.6 ns t peh clock to pktend hold time 0 ns t xflg clock to flags output propagation delay 9.5 ns table 19. slave fifo synchronous packet end strobe parameters with externally sourced ifclk [10] parameter description min max unit t ifclk ifclk period 20.83 200 ns t spe pktend to clock setup time 8.6 ns t peh clock to pktend hold time 3.04 ns t xflg clock to flags output propagation delay 13.5 ns [+] feedback
cy7c68053 document # 001-06120 rev *j page 30 of 42 there is no specific timing requirement to be met for asserting the pktend pin with regards to asserting slwr. pktend can be asserted with the last data value clocked into the fifos or thereafter. the only consideratio n is that the setup time t spe and the hold time t peh must be met. although there are no specific timing requirements for the pktend assertion, there is a specif ic corner case condition that needs attention while using the pktend to commit a one byte/word packet. there is an additional timing requirement to be met when the fifo is configured to operate in auto mode and you want to send two packets back to back: a full packet (full defined as the number of bytes in the fifo meeting the level set in autoinlen register) committed automatically followed by a short one byte/word packet committed manually using the pktend pin. in this scenario, make sure to assert pktend at least one clock cycle after the risi ng edge that c aused the last byte/word to be clocked into the previous auto committed packet. figure 14 shows this scenario. x is the value the autoinlen register is set to when the in endpoint is configured to be in auto mode. figure 14 shows a scenario where two packets are committed. the first packet is committed automatically when the number of bytes in the fifo reaches x (value set in autoinlen register) and the second one byte/word short packet is committed manually using pktend. note that there is at least one ifclk cycle timing between the assertio n of pktend and clocking of the last byte of the previous packet (causing the packet to be committed automatically). failing to adhere to this timing, results in the fx2lp18 failing to send the one byte/word short packet. 9.8 slave fifo asynchronous packet end strobe table 20. slave fifo asynchronous packet end strobe parameters [19] parameter description min max unit t pepwl pktend pulse width low 50 ns t pwpwh pktend pulse width high 50 ns t xflg pktend to flags output propagation delay 115 ns ifclk slwr data figure 14. slave fifo synchronous write sequence and timing diagram [16] t ifclk >= t swr >= t wrh x-2 pktend x-3 t fah t spe t peh fifoadr t sfd t sfd t sfd x-4 t fdh t fdh t fdh t sfa 1 x t sfd t sfd t sfd x-1 t fdh t fdh t fdh at least one ifclk cycle flags t xflg pktend t pepwl t pepwh figure 15. slave fifo asynchronous packet end strobe timing diagram [16] [+] feedback
cy7c68053 document # 001-06120 rev *j page 31 of 42 9.9 slave fifo output enable 9.10 slave fifo ad dress to flags/data table 21. slave fifo output enable parameters parameter description min max unit t oeon sloe assert to fifo data output 10.5 ns t oeoff sloe deassert to fifo data hold 2.15 10.5 ns table 22. slave fifo address to flags/data parameters parameter description min max unit t xflg fifoadr[1:0] to flags out put propagation delay 10.7 ns t xfd fifoadr[1:0] to fifo data output propagation delay 14.3 ns sloe data t oeon t oeoff figure 16. slave fifo output enable timing diagram [16] fifoadr [1.0] data t xflg t xfd flags nn+1 figure 17. slave fifo address to flags/data timing diagram [16] [+] feedback
cy7c68053 document # 001-06120 rev *j page 32 of 42 9.11 slave fifo synchronous address 9.12 slave fifo asynchronous address table 23. slave fifo synchronous address parameters [10] parameter description min max unit t ifclk interface clock period 20.83 200 ns t sfa fifoadr[1:0] to cl ock setup time 25 ns t fah clock to fifoadr[1:0] hold time 10 ns slave fifo asynchronous address parameters [19] parameter description min max unit t sfa fifoadr[1:0] to slrd/sl wr/pktend setup time 10 ns t fah rd/wr/pktend to fifoa dr[1:0] hold time 10 ns ifclk slcs/fifoadr [1:0] t sfa t fah figure 18. slave fifo synchronous address timing diagram [16] slrd/slwr/pktend slcs/fifoadr [1:0] t sfa t fah figure 19. slave fifo asynchronous address timing diagram [16] [+] feedback
cy7c68053 document # 001-06120 rev *j page 33 of 42 9.13 sequence diagram various sequence diagrams and exampl es are presented in this section. 9.13.1 single and burst synchronous read example figure 20 shows the timing relationship of the slave fifo signals during a synchronous fifo read using ifclk as the synchronizing clock. the diagram illustrates a single read followed by a burst read. at t = 0 the fifo address is stable and the signal slcs is asserted (slcs may be tied low in some applications). note t sfa has a minimum of 25 ns. this means that when ifclk is running at 48 mhz, th e fifo address setup time is more than one ifclk cycle. at t = 1, sloe is asserted. sloe is an output enable only whose sole function is to drive the data bus. the data that is driven on the bus is the data that the internal fifo pointer is currently pointing to. in this exampl e, it is the first data value in the fifo. note the data is prefetched an d driven on the bus when sloe is asserted. at t = 2, slrd is asserted. slrd must meet the setup time of t srd (time from asserting the slrd signal to the rising edge of the ifclk) and maintain a minimum hold time of t rdh (time from the ifclk edge to the de assertion of the slrd signal). if the slcs signal is used, it must be asserted before slrd (that is, the slcs and slrd signals must both be asserted to start a valid read condition). the fifo pointer is updated on t he rising edge of the ifclk while slrd is asserted. this starts the propagation of data from the newly addressed location to the data bus. after a propagation delay of t xfd (measured from the rising edge of ifclk) the new data value is present. n is the first data value read from the fifo. to have data on the fifo data bus, sloe must also be asserted. the same sequence of events is shown for a burst read and is marked with the time indicators of t = 0 through 5. note for the burst mode, the slrd and sloe are left asserted during the entire duration of the read. in the burst read mode, when sloe is asserted, data indexed by the fifo pointer is on the data bus. during the first read cycle on the rising edge of the clock, the fifo pointer is updated and increments to point to address n+1. for each subsequent rising edge of ifclk while the slrd is asserted, the fifo pointer is incremented and the next data value is placed on the data bus. ifclk slrd flags sloe data figure 20. slave fifo synchronous read sequence and timing diagram [16] t srd t rdh t oeon t xfd t xflg t ifclk n+1 data driven: n >= t srd t oeon t xfd n+2 t xfd t xfd >= t rdh t oeoff n+4 n+3 t oeoff t sfa t fah fifoadr slcs t=0 n+1 t=1 t=2 t=3 t=4 t fah t=0 t sfa t=1 t=2 t=3 t=4 nn n+1 n+2 fifo pointer n+3 fifo data bus n+4 not driven driven: n sloe slrd n+1 n+2 n+3 not driven slrd sloe ifclk figure 21. slave fifo synchronous sequence of events diagram ifclk ifclk ifclk ifclk n+4 n+4 ifclk ifclk ifclk ifclk slrd n+1 slrd n+1 n+1 sloe not driven n+4 n+4 ifclk sloe [+] feedback
cy7c68053 document # 001-06120 rev *j page 34 of 42 9.13.2 single and burst synchronous write figure 22 shows the timing relationship of the slave fifo signals during a synchronous write using ifclk as the synchronizing clock. the diagram illustrates a single write followed by burst write of 3 bytes and committing all 4 bytes as a short packet using the pktend pin. at t = 0 the fifo address is stable and the signal slcs is asserted. (slcs may be tied low in some applications) note t sfa has a minimum of 25 ns. this means that when ifclk is running at 48 mhz, th e fifo address setup time is more than one ifclk cycle. at t = 1, the external master/peripheral must output the data value onto the data bus with a minimum setup time of t sfd before the rising edge of ifclk. at t = 2, slwr is asserted. the slwr must meet the setup time of t swr (time from asserting the slwr signal to the rising edge of ifclk) and maintain a minimum hold time of t wrh (time from the ifclk edge to the deassertion of the slwr signal). if the slcs signal is used, it must be asserted before slwr is asserted. (that is, the slcs and slwr signals must both be asserted to start a valid write condition). while the slwr is asserted, data is written to the fifo and on the rising edge of the ifclk, t he fifo pointer is incremented. the fifo flag is also updated after a delay of t xflg from the rising edge of the clock. the same sequence of events is also shown for a burst write and is marked with the time indicators of t = 0 through 5. note for the burst mode, slwr and slcs are left asserted for the entire duration of writing all th e required data values. in this burst write mode, when the slwr is asserted, the data on the fifo data bus is written to th e fifo on every rising edge of ifclk. the fifo pointer is updated on each rising edge of ifclk. in figure 22 , when the four bytes are written to the fifo, slwr is deasserted. the short 4-byte packet can be committed to the host by asserting the pktend signal. there is no specific timing requirement that needs to be met for asserting the pktend signal with regards to asserting the slwr signal. pktend can be asserted with the last data value or thereafter. the only requirement is that the setup time t spe and the hold time t peh must be met. in the scenario of figure 22 , the number of data values committed includes the last value written to the fifo. in this example, both the data value and the pktend signal are clocked on the same rising edge of ifclk. pktend can also be asserted in subsequent clock cycles. the fifoaddr lines must be held co nstant during the pktend assertion. although there are no specific timing requirements for the pktend assertion, there is a specif ic corner case condition that needs attention while using the pktend to commit a one byte/word packet. additional timing requirements exist when the fifo is configured to operate in au to mode and you want to send two packets: a full packet (full defined as the number of bytes in the fifo meeting the level set in autoinlen register) committed automatically followed by a short one byte/word packet committed manually using the pktend pin. in this case, the external master must make sure to assert the pktend pin at least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet (the packet with the number of bytes equal to what is set in the autoinlen register). refer to figure 14 on page 30 for further details about this timing. ifclk slwr flags data figure 22. slave fifo synchronou s write sequence and timing diagram [16] t swr t wrh t sfd t xflg t ifclk n >= t swr >= t wrh n+3 pktend n+2 t xflg t sfa t fah t spe t peh fifoadr slcs t sfd t sfd t sfd n+1 t fdh t fdh t fdh t fdh t=0 t=1 t=2 t=3 t sfa t fah t=1 t=0 t=2 t=5 t=3 t=4 [+] feedback
cy7c68053 document # 001-06120 rev *j page 35 of 42 9.13.3 sequence diagram of a single and burst asynchronous read figure 23 illustrates the timing relationship of the slave fifo signals during an asynchronous fifo read. it shows a single read followed by a burst read. at t = 0, the fifo address is stable and the slcs signal is asserted. at t = 1, sloe is asserted. this results in the data bus being driven. the data that is driven on to the bus is previous data; it is data that was in the fifo from a prior read cycle. at t = 2, slrd is asserted. the slrd must meet the minimum active pulse of t rdpwl and minimum inactive pulse width of t rdpwh . if slcs is used then, slcs must be asserted before slrd is asserted (that is, the slcs and slrd signals must both be asserted to start a valid read condition). the data that is driven, after asserting slrd, is the updated data from the fifo. this data is valid after a propagation delay of t xfd from the activating edge of slrd. in figure 23 , data n is the first valid data read from the fifo. for data to appear on the data bus during the read cycl e (for example, slrd is asserted), sloe must be in an asserted state. slrd and sloe can also be tied together. the same sequence of events is also shown for a burst read marked with t = 0 through 5. note in burst read mode, during sloe assertion, the data bus is in a driven state and outputs the previous data. once slrd is asserted, the data from the fifo is driven on the data bus (sloe must also be asserted) and then the fifo pointer is incremented. slrd flags sloe data figure 23. slave fifo asynchronous read sequence and timing diagram [16] t rdpwh t rdpwl t oeon t xfd t xflg n data (x) t xfd n+1 t xfd t oeoff n+3 n+2 t oeoff t xflg t sfa t fah fifoadr slcs driven t xfd t oeon t rdpwh t rdpwl t rdpwh t rdpwl t rdpwh t rdpwl t fah t sfa n t=0 t=0 t=1 t=7 t=2 t=3 t=4 t=5 t=6 t=1 t=2 t=3 t=4 nn sloe slrd fifo pointer n+3 fifo data bus not driven driven: x n not driven sloe n n+2 n+3 figure 24. slave fifo asynchronous read sequence of events diagram slrd n n+1 slrd n+1 slrd n+1 n+2 slrd n+2 slrd n+2 n+1 sloe not driven sloe n n+1 n+1 [+] feedback
cy7c68053 document # 001-06120 rev *j page 36 of 42 9.13.4 sequence diagram of a sing le and burst asynchronous write figure 25 illustrates the timing relationship of the slave fifo write in an asynchronous mode. the diagram shows a single write followed by a burst write of 3 bytes and committing the 4-byte-short packet using pktend. at t = 0 the fifo address is applie d, ensuring that it meets the setup time of t sfa . if slcs is used, it must also be asserted (slcs may be tied low in some applications). at t = 1 slwr is asserted. slwr must meet the minimum active pulse of t wrpwl and minimum inactive pulse width of t wrpwh . if the slcs is used, it must be asserted before slwr is asserted. at t = 2, data must be present on the bus t sfd before the deasserting edge of slwr. at t = 3, deasserting slwr causes the data to be written from the data bus to the fifo and then the fifo pointer is incremented. the fifo flag is also updated after t xflg from the deasserting edge of slwr. the same sequence of events is shown for a burst write and is indicated by the timing marks of t = 0 through 5. note in the burst write mode, once slwr is deasserted, the data is written to the fifo and then the fifo pointer is incremented to the next byte in the fifo . the fifo pointer is post incremented. in figure 25 when the four bytes are written to the fifo and slwr is deasserted, the short 4-byte packet can be committed to the host using the pktend. the external device must be designed to not assert slwr and the pktend signal at the same time. it must be designed to assert the pktend after slwr is deasserted and meet the minimum deasserted pulse width. the fifoaddr lines are to be held constant during the pktend assertion. pktend slwr flags data figure 25. slave fifo asynchronous write sequence and timing diagram [16] t wrpwh t wrpwl t xflg n t sfd n+1 t xflg t sfa t fah fifoadr slcs t wrpwh t wrpwl t wrpwh t wrpwl t wrpwh t wrpwl t fah t sfa t fdh t sfd n+2 t fdh t sfd n+3 t fdh t sfd t fdh t pepwh t pepwl t=0 t=2 t =1 t=3 t=0 t=2 t=1 t=3 t=6 t=9 t=5 t=8 t=4 t=7 [+] feedback
cy7c68053 document # 001-06120 rev *j page 37 of 42 10. ordering information ta b l e 2 4 lists the key package features and ordering codes. the table co ntains only the parts that are currently available. if you do not see what you are looking for, contact your local sales repr esentative. for more information, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products . ordering code definitions table 24. key features and ordering information ordering code package type ram size number of prog i/os 8051 address/data buses CY7C68053-56BAXI 56 vf bga? pb-free 16 k 24 ? development tool kit cy3687 mobl-usb fx2lp18 development kit cy marketing code: 7 = cypress products 7 c 68 technology code: c = cmos company id: cy = cypress xxxx family code: 68 = usb part number - 56bax package type: 56-pin vfbga pb-free (c, i) thermal rating: c = commercial i = industrial (t) tape and reel [+] feedback
cy7c68053 document # 001-06120 rev *j page 38 of 42 11. package diagram the fx2lp18 is available in a 56-pin vfbga package. figure 26. 56 vfbga (5 5 1.0 mm) 0.50 pitch, 0.30 ball bz56 [+] feedback [+] feedback 001-03901 *c [+] feedback
cy7c68053 document # 001-06120 rev *j page 39 of 42 12. pcb layout recommendations the following recommendations must be followed to ensure reliable high performance operation. at least a four-layer impedance controlled board is required to maintain signal quality. specify impedance targets (ask your board vendor what they can achieve). to control impedance, maintain trace widths and trace spacing to within specifications. minimize stubs to minimize reflected signals. connections between the usb connector shell and signal ground must be done near the usb connector. bypass or flyback caps on vbus, near connector, are recommended. dplus and dminus trace lengths must be kept within 2 mm of each other in length, with preferred length of 20 to 30 mm. maintain a solid ground plane under the dplus and dminus traces. do not allow the plane to be split under these traces. it is preferable to have no vias placed on the dplus or dminus trace routing. isolate the dplus and dminus tr aces from all other signal traces by no less than 10 mm. [+] feedback
cy7c68053 document # 001-06120 rev *j page 40 of 42 13. acronyms 14. document conventions units of measure table 25. acronyms used in this document acronym description ata advanced technology attachment asic application specific integrated circuit cpu central processing unit did device identifier dsp digital signal processor eeprom electrically erasable programmable read only memory epp enhanced parallel port ecc error correction code fifo first in first out gpif general programmable interface gpio general purpose input / output i/o input output i2c inter integrrate circuit pda personal digital assistant pll phase lock loop pid product identifier ram random access memory sie serial interface engine sof start of frame usb universal serial bus vid vendor identifier vfbga very fine ball grid array utopia universal test and operations physical-layer table 26. units of measure symbol unit of measure khz kilohertz mbytes megabytes mhz megahertz a microampere s microseconds w microwatts ma milliampere mw milliwatts ns nanoseconds ppm parts per million pf picofarads vvolts [+] feedback
cy7c68053 document # 001-06120 rev *j page 41 of 42 document history page document title: cy7c68053 mobl-usb? fx2lp18 usb microcontroller document number: 001-06120 revision ecn orig. of change submission date description of change ** 430449 osg 03/03/06 new data sheet *a 434754 osg 03/24/06 in section 3.3, stated t hat scl and sda pins can be connected to v cc or v cc_io chnged sections 3.5, 3.18.1 and pin descri ptions of scl, sda to indicate that since discon=1 after reset, an eeprom or eeprom emulation is required on the i 2 c interface in pin description table, renamed pin 2h (reserved) to ground in section 6, added statement ?the gpio?s are not over voltage tolerant, except the scl and sda pins, wh ich are 3.3 v tolerant? in section 8,added a footnote to the dc char table stating that avcc can be floated in low power mode in section 8, changed v ih max in dc char table from 3.6 v to v cc_io + 10% *b 465471 osg see ecn changed the recommendation for the pull up resistors on i 2 c split icc into 4 different values, corresponding to the different voltage supplies changed isus typical to 20ua and 220ua added section 3.9.3 on susp end current considerations *c 484726 ari see ecn removed all references the part number cy7c68055. corrected the bullet in features to state that 24 gpio?s are available. added the test id (tid#) to the features on the front page. made changes to the block diagram on the first page (this is now a visio drawing instead of a framemaker drawing). corrected the ambient temperature with power supplied. moved figure titles to meet the new template. checked grammar. took out 9-bit address bus from the block diagram on the first page. corrected figure 4.1 *d 492009 osg see ecn added icc data in dc characteristics and maximum power dissipation *e 500408 osg see ecn changed esd spec to 1500 v *f 502115 osg see ecn changed esd spec to 2000 v and 1500 v only for scl and sda pins. added min spec for t oeoff changed icc and power dissipation numbers *g 1128404 osg/ari see ecn removed slcs from figure in section 9.6 slave fi fo asynchronous write changed slwr pulse high parameter to 50ns section 9.13.1 9 v removed the indication that slcs and slrd can be asserted together section 9.13.3 - removed the indicati on that slcs and slrd can be asserted together implemented the latest template. *h 1349903 aesa see ecn section 7 - changed -0c to -40c *i 2728476 odc 07/02/09 deleted note on avcc parameter in dc characteristics table *j 3072698 odc 10/27/10 template update and styles update. included table of contents, ordering code definitions, acronyms, and units of measure. updated package diagram revision from *b to *c. [+] feedback
document # 001-06120 rev *j revised october 28, 2010 page 42 of 42 purchase of i2c components from cypress, or one of its sublic ensed associated companies, conveys a license under the philips i2 c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by philips. mobl-usb fx2lp18, ez-usb fx2lp and renumerati on are trademarks, and mobl-usb is a registered trademark, of cypress semiconductor corporation. all product and company names mentioned in this document are the trademarks of their resp ective holders. cy7c68053 ? cypress semiconductor corporation, 2006-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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